USB PD 3.0 new BMC decoding circuit
Aiming at the shortcomings of traditional BMC decoding in USB PD 3.0 protocol, such as high power consumption, large area and poor anti-interference, a new decoding system with low power consumption, small area and strong robustness with automatic correction function is proposed. The system makes full use of the advantages of FIR filter algorithm and sliding average filter algorithm, so that it can better serve the decoding system, in addition, the system also increased the signal monitoring function. To verify the reliability of the system, Verilog language was used to describe the system circuit and simulate it in DC development platform of Synopsys. The experimental results show that compared with the traditional decoding circuit, the robustness of the system is obviously enhanced under the same conditions, while the area is reduced by 2.19% and the power consumption is reduced by 2.06%, which fully reflects the advantages of low power consumption, small area and strong anti-interference ability. The system lays a theoretical foundation for improving the reliability and practicality of USB PD quick charging chip design, and also improves the charging efficiency of USB PD 3.0.
With the rapid development of smart phones, the current mainstream fast charging protocols include Huawei SCP, Qualcomm QC, Samsung AFC, OPPO VOOC, and USB BC1.2. In order to unify the technical specifications for rapid charging, the USB-IF Association defines the USB PD3.0 protocol, which not only solves the problem of device and charger switching from one-to-one to many-to-one, but also reduces the consumption cost for consumers. At present, major chip manufacturers pay more and more attention to the design of USBPD quick charging chip, and one after another invest in the research based on USBPD protocol, in order to grab the quick charging device market as soon as possible. USB PD BMC codec is one of the core technology of the agreement, one was BMC coding to the clock and data included in the data stream, at the same time of data message, will also be clock synchronization information to each other, and at least once during each coding level, there is no dc component, therefore has the synchronization and the certain anti-interference ability. The receiver USES the synchronization of BMC coding to lock its own clock frequency for efficient and accurate communication. Coding rules, data level 0 is not flipped, data level 1 is flipped, because this three-quarters UI is used as a criterion to determine whether data level 0 or data 1 is received. BMC decoding is divided into leading code decoding and data decoding. The leading code data is 64bit 0101... , the data can only be decoded after the current guide code is correct. If the decoding performance of the leading code is too poor, the data decoding will be wrong. Therefore, this paper analyzes the shortcomings of traditional decoding circuit, such as large area, high power consumption and weak anti-interference ability, and proposes a new decoding circuit system with high performance.
The structure block diagram of traditional BMC decoding system is composed of filtering module, edge detection module, decoding module and output module. A traditional BMC decoding circuit system is proposed, which USES a high-speed clock to oversample the 64bit leading code, and the sampling value is Counter_total. The decoding threshold Th is solved by arithmetic mean algorithm, as shown in Formula 1. If the edge arrival of data is detected within Th, the solved code is 1; if no edge arrival is detected within Th, the solved code is 0. If the length of the leading code is lower than 64BIT, this algorithm will mistake the effective data for the leading code, thus resulting in low robustness and poor anti-interference ability of the circuit. In addition, the oversampling of 64BIT not only increases the computational burden of the circuit, but also increases the area and power consumption of the circuit.
In the flow chart of traditional BMC decoding design, the signals on THE CC line of type-C interface are filtered to eliminate the burrs on the signals. Then the 64bit leading codes are oversampled and the total count is obtained, and then the decoding threshold is calculated. Once the 64bit leading code oversampling is completed, the data after the 64bit leading code will be oversampled, and the data after the leading code will be extracted according to the decoding threshold.
The new BMC decoding structure is composed of filter module, BMC decoding module, expected decoding module, calibration module and output module. Its basic principle is as follows, filtering module filter Type - C interface CC line burr, guarantee the stability of the input data, then the stability of data transmission to the BMC decoding module, through the module of the algorithm to work out the input data and to calibration module, at the same time, to determine lead code 2 bit belong to which Type, then work out effective transmit the data to 1 bit of decoding module, decoding module after receiving the valid data is expected to forecast the next data exist in the current registers, and forecast the last calibration module, transmit the data to At this point, the correction module judges that the extracted data is compared with the predicted data. If the comparison results are consistent, the decoded data is transmitted to the sending module. If not consistent, the circuit will be reset.
New flow chart of BMC decoding structure, the CC line data signal filtering, eliminate the burr on the data signals, by 2 in the leading code bit determine belong to which kinds of form, and it is concluded that decoding threshold, once 2 bit type judgment, can according to the lead code 0 s and 1 s in the rules of changes alternately can infer the next bit of the predictive value of 0 or 1. After the type of the 2bit in the leading code is determined, every 8bit after the 2bit will be divided into a group for decoding. The process is as follows: According to lead code 2 bit decoding threshold to lead code after 2 bit in the first group of 8 bit lead code decoding, and it is concluded that the new decoding threshold, at the same time will be the first group to work out the lead code comparing with predictive value, if is consistent, then decode correctly, this group number plus 1, if the group number less than or equal to 4, a new decoding threshold for a second set of 8 bit lead code decoding and collect samples, again updated decoding threshold, at this point the second group of decoding results comparing with predictive value, if the group will be inconsistent number plus 1, inconsistent, Circuit reset and re-test the form of the 2bit before the circuit's leading code, and restart the above process. Once the four sets of 8BIT leading codes are correctly solved, the circuit is stable, and the final decoding threshold can be used to decode the following leading codes or data. In the decoding process of the leading codes after 4 groups of 8 bits, only 0.75UI is required to be oversampled. In the process of oversampling, if edge change is detected within the range of 0.75UI, 1 is detected; otherwise, 0 is detected. Once 1 or 0 is detected, the remaining 0.25UI does not need to be oversampled and the value of the next bit leading code is decoded directly. When decoding the next leading code, it is also oversamped within the range of 0.75UI and detects whether there is edge change, so as to detect 0 or 1. The remaining 0.25UI does not need oversampling and directly jumps to the following leading code for detection, and so on (Opinion 3). In addition, compared with the traditional method, the new BMC decoding has the function of automatic correction, which enables the circuit to reset immediately in the case of abnormal decoding, and ensures the reliability of the circuit. In terms of area and power consumption, the new BMC decoding is lower than the traditional decoding. The modules in the block diagram of the new BMC decoding structure are introduced.
The filter module conducts FIR filtering for the input data on THE CC line of type-C interface. FIR filter is the basic structure. The data from type-C interface will have burrs, so the burrs will be filtered out by FIR filter scheme. The formula of FIR filter is shown in 2. The tap coefficient of the filter is 1/8 and the order of the filter is 7. Every seven groups can determine whether the CC line is real data or burr, so as to improve the decoding accuracy.
Bmc_data_filtered is the signal filtered by the filter module after filtering the burrs on CC line. The circuit mainly determines which form 2bit belongs to in the leading code, and there are three forms in total. Due to the use of Clk_18M clock to do the edge detection after the count value has a large and small. If a is less than C, b less than C means 0 and 1 start, if A is greater than B, a greater than C means 1 and 0 start, 9. If C is greater than C, b greater than A means missing 1 start. This method avoids the disadvantage of decoding only at the beginning of the leading code and greatly increases the reliability and robustness of the circuit. The rising and falling edge of bMC_DATa_Filtered signals are obtained after two beats or operation. Equal1 determines the height of BMC_DATa_Filtered signals. If it is high, Add1 will be triggered; if it is low, Add0 will be triggered; and the value of adder is stored in the register. Meanwhile, the training_start signal is output. At the same time, the calculated value of 2bit is divided by the output of 2. At this time, the counter is the value of 1UI.
Decoding threshold module circuit: The ymain signal represents 0.75UI, and the reamble8_counter signal represents the first group of 8bit data. After the completion of the 2BIT detection in the leading code, the decoding begins. At this point, the symbol signal training_start that starts decoding is raised. The length of the high and low level can be determined by the first 2 bits of data in the leading code, and the counter value of 1UI can be calculated and used as a benchmark to solve the first group of 8bit data. At the same time, 18M clock is used to sample the first set of 8BIT signals on CC line and count the high and low levels of the data. The count value of the high level count is stored in the H_TEMp register, and the count value of the low level count is stored in the L_temp register, and the Counter_First8 can be obtained. The first 2 bits of data in the leading code are used to solve the counter value of 1UI, and the counter is multiplied by 3/4 result for the decoding module to solve. 8 bit data such as solution out after decoding threshold module to update the UI count value, using the moving average filtering algorithm is a formula, is a set of 8 bit on the high and low electric flat count together with lead code in the first 2 1 UI value multiplied by 8 bit calculate, finally the results divided by 16, calculate the result is the new UI count, and the value of 0.75 UI is decoding threshold ymain, ymain values is the basis of the second set of data decoding.
The second set of 8bit data is then solved with the ymain value as the benchmark, and the second set of high and low level count values are stored in Counter_Second8 register. The UI count value and ymain value are then updated to prepare for solving the third set of data, and so the decoding threshold for the third and fourth sets can be determined. Equal2 is carried out on the edge of bmc_data_filtered signal of counting and judgment, 12 shows that detects when a group of 8 bits of data, the reamble8_counter counter plus 1, Equal3 for judgment of reamble8_counter 2 gate multiplier multiples for 1/16 of the pathway, for gate 3 multiples multiplier for two-thirds of the pathway, 4 gating multiplier multiples for 1/2 pathway, multiplier ratio can be found for 1/16 is a reuse logic. This method not only reduces the area but also reduces the circuit power consumption, reduces the manufacturing cost and improves the circuit performance.
The decoding module circuit is within the ymain value. If edge hopping is detected, the decoding is to 1; if edge hopping is not detected within ymain, the decoding is to 0. Equal3 is to determine whether the value of reamble8_counter is 4, is the stop-update decoding threshold of 4, and the decoding threshold is the final decoding threshold. Where Equal2 is inside ymain, whether edge change is detected.
The expected decoding module is based on the leading code data of 64BIT 0101...... And the next leading code data value can be obtained from the current data. The detection of 0 or 1 can determine whether the next decoded data is 1 or 0 and thus predict the next leading code decoded data. The leading code data extracted by the correction module will be compared with the expected leading code data. For example, the current correct data is 0, and the decoded data should be 1 according to the protocol specification. If the decoded data is 0 at this time, a reset signal will be generated inside the circuit to reset the circuit and redecode. Only when the circuit accurately solves the first 32 bits of data in the leading code can it be determined that the possibility of failure in the decoding process of the circuit is very, very low, so as to improve the accuracy of the decoded data. The output module is to register output the solved data. Since the register output is a sequential circuit, it can greatly reduce the probability of burr output, avoid the generation of metastable state, and thus avoid the paralysis of the circuit. In this algorithm, a correction module is added, in which the BMC decoding module and the expected decoding module output values are compared accordingly, so as to improve the decoding accuracy.
The traditional algorithm can correctly decode only when the leading code is 64bit, but if the leading code is less than 64bit, the decoding problem will occur in the traditional design scheme when the leading code is 50bit. Among them, Clk_50M signal is 50M clock; DECODE_data signal represents abnormal decoded signals; BMC_DATa_FILTERED signal represents data signals to be decoded; when BMC_DATa_FILTERED signal is 0, decoDE_data signal solved is 1.
0.75 UI value calculation, now account for part of the signal as follows, bmc_data_filtered said CC line data for the signal after filtering, training_start up before bmc_data_filtered signal is in the lead code 2 bit detection, stop_count_12edges said 12 edges detected after this will generate a pulse signal, said it had detected 8 bit data, h_temp said CC line 18 m high level need how many clock cycles, L_temp represents how many 18M clock cycles are required for low levels on CC lines. The XValue signal represents the superposition of high and low level meter values on the CC line. Xmain signal means the sum of the high and low level meter values of the previous group and the high and low level meter values of this group of CC lines, and boTH_edge signal means the rising edge and falling edge of the data on CC lines are detected. The first 2 bits of the leading code count 23+25+51=99, that is to say, the count value of a UI is 99/2=49,0.75UI=36, and the value of ymain is 36. The first set of 8BIT high and low level meter values and is 396, because the first set of 8BIT data should be solved by including the first 2 bits of the leading code, that is, the UI calculated by the first 2 bits in the leading code is taken as the benchmark to solve the first set of 8bit data. The UI value of the second set of 8bit data is to add the 396 of the first set of 8-bit Xmain and the 49*8 of the leading code, divide the result by 2 to get the total value of the second set of 8bit, and get the value of one UI and 0.75UI, so as to solve the second set of 8bit data, and so on, solve the third group, the fourth group, and so on.
After the 2bit in the leading code is determined, the following data can then be predicted, because the USB PD3.0 protocol stipulates that the data headers are in the form of alternating 64bit 0 and 1, so as long as the leading code is determined, the following code can be predicted.
The predicted_data signal is the prediction signal. For example, if the data solved at the beginning is 1, the next data can be predicted to be 0. If the predicted data is consistent with the solved data, it can be sure that the data decoding is correct; if the solved data is inconsistent with the predicted data, it will be reset and the decoding will start again. And so on, until the 32-bit data is completely solved. If the 32 bits of data are decoded without any problems, it can be determined that the circuit is indeed stable, and the subsequent prediction circuit will not work, thus reducing power consumption.
Clk_18M signal is the decoded master clock, and the frequency must be 60 times higher than the data on CC line. According to the over-sampling theorem, in the process of analog or digital signal conversion, when the sampling frequency Fmax is greater than the highest frequency fmax in the signal, the digital signal after sampling will completely retain the information in the original signal. The syn_RSTN signal is that the predicted data is inconsistent with the extracted data, and this signal is pulled down for reset, otherwise it remains high. The BMC_data_filered signal is the filtered data on the CC line. Decode_data signal is the decoded data, and the predicted_data signal is the predicted data.
In the design process, the area and power consumption of the chip should be taken into account. Reducing the area and power consumption of the chip without affecting the performance not only reduces the manufacturing cost of the chip, but also improves the performance of the chip. Using DC tool analysis, the new BMC decoding method is 2.19% lower in area and 2.06% lower in power consumption than the traditional method. The comparison results of the two methods are shown in Table 1. DC evaluates the power consumption of the circuit implementation logic itself, which is different from the actual operation power. In fact, the reduced power consumption of this design is more than 2.06% as shown in Table 1. The above reasons are analyzed as follows. The traditional method USES high-speed 50M clock to decode BMC signals, while the new method USES low-frequency clock 18M. The traditional method counts the high and low level of the leading code 64bit and divides the counting value by 64 to obtain the value of 1UI. However, the new method only needs to count the high and low level of 8bit to obtain 1UI, and the number of registers for these counting values is smaller than that of the traditional method. Traditional method to count the results divided by 64, it will cost a lot of resources, and the new method USES the reuse logic circuits, this greatly drop low area resources, the new method increased the correction module with the expected decoding module, calibration module is basically adopts the combinational logic comparator, expected the decoding module used the temporal logic, while using temporal logic, but is a single bit signal timing operation, therefore, less occupied area. Among them, the calibration module and the expected decoding module will not continue to work after the completion of four sets of leading code detection circuits, thus reducing the power consumption in the circuit operation. New methods in four groups lead code detection circuit is completed by the final decoding threshold sampling have been carried out to the lead code behind to decode, in just a sampling of samples have been carried out to 0.75 UI can judge the lead code is 0 or 1, the new method of the remaining 30 in the lead to 64 - bit code bit multiplied by 0.25 part don't need a sample logic, and the traditional 64 - bit all need sampling logic. To sum up, the new BMC decoding method has smaller area and lower power consumption than the traditional method.
The new BMC decoder is better than the traditional BMC decoder in anti-interference and anti-interference. Because the traditional design scheme is based on 64bit leading code to get the decoding threshold. If there is only 50bit leading code, the traditional design scheme will have decoding problems. The traditional algorithm misunderstands the data 100 out of 110, such as signal DECOde_data_OLD, while the new algorithm can restore the data signal 100 out of error, such as decode_data_new signal. Lead code in traditional method is less than 64 bit will be decoded the cause of the error analysis is as follows, the traditional method first, high and low level meter numerical statistics, once detected 96 input signal edge, suggest that lead code 64 - bit have statistical end, so will get 1 UI value statistics, divided by 64, the 64 - bit is 0 and 1 alternating if lead code missing, assuming that only 50 bit, traditional method will be part of the data as a lead code, such as the edge of the counter meter 96, statistics at this time than 64 bit lead code statistics, small or large, Therefore, 1UI value and decoding threshold will be inaccurate, resulting in incorrect decoded data.
This paper analyzes the shortcomings of traditional decoding circuit, such as high power consumption, large area, no correction function and poor anti-interference performance, and proposes a new BMC decoding design with strong robustness, low power consumption, small area and automatic correction function. This circuit adopts filtering algorithm and sliding average algorithm, and adds correction module to improve the robustness of circuit. The research shows that the circuit is more complete than the traditional design in function, but also reduces the chip area and power consumption, making the manufacturing cost greatly reduced. The design circuit is not complicated in terms of BMC codec principle, but it is not easy to design a reliable hardware circuit. After all, not only safety reliability, but also power consumption and area of the circuit should be taken into consideration when designing the circuit. For further research, the later work is how to apply this circuit to USB PD chip.