FPGA online upgrade method based on USB interface
In a variety of application environments, it is not allowed to use JTAG downloader to upgrade the program of programmable devices, and it is required to realize the online upgrade of programmable devices through the external communication interface of the device. For the FPGA chip and its configuration chip of XILINX company, an online program upgrade method based on USB interface is proposed. The USB2.0 interface is an interface that is extended on the FPGA to communicate with the upper computer. By cooperating with the upper computer software, the FPGA configuration chip is erased and programmed to realize the online upgrade of the FPGA program. This paper presents the upgrading principle and method of this method.
Field programmable gate array (FPGA), with extremely high flexibility and parallel processing capacity, is widely used in medical equipment, industrial control, instrumentation and other fields. FPGA program code is generally stored in FLASH PROM with chip, and the most common method for FPGA programming is to use special download software (provided by FPGA manufacturer) to write programs through JTAG interface. However, in a variety of application environments, the JTAG interface is not allowed to be extracted from the device shell. In order to update the FPGA program, it is necessary to disassemble the device or even the whole machine on the spot. Using JTAG interface to burn and write programs is not convenient, but also increases the maintenance cost of equipment greatly.
USB cable universal serial bus is a kind of interface technology applied in the computer field. USB interface has the characteristics of faster transmission speed, support for hot plugging and connecting multiple devices, and has been widely used in all kinds of external devices. CY7C68013A is CYPRESS company design a USB controller, has a large capacity FIFO for data buffer, as from a device can be used when synchronous or asynchronous FIFO way connected with the controller, realizing the communication channel between the controller and the upper machine, the user can without a thorough understanding of USB interface, with the development of USB interface.
Based on the USB2.0 interface developed by ourselves in a certain device, this paper proposes a method to upgrade the FPGA chip of XILINX company online through the USB2.0 interface without adding hardware, and presents the upgrading principle and method of this method.
XILINX FPGA device company when use are based on a FPGA chip and a configuration, configuration chip has a variety of choice, the configuration way also have many choices, 4 series of tests on Virtex XC4VLX25 and Flash PROM XCF08P, for example, using the JTAG interface will be connected, the configuration and the FPGA chip is the JTAG interface TDI signal in the configuration of the chip TDI interface, the configuration of the chip TDO interface is linked with TDI of FPGA, FPGA TDO is connected with the JTAG interface of TDO again, In the form of Daisy chain, TMS and TCK are directly connected. When using the JTAG download line, you can scan the JTAG link in the ISE software and realize the burn and write of the configuration chip.
This design selects CY7C68013A from CYPRESS, which belongs to EZ_USB FX2LP series, a low power USB2.0 microcontroller. It includes modules such as an enhanced 8051 processor, 16KB on-chip RAM, a USB transceiver, a serial interface engine SIE, 4KB FIFO memory, and a universal programmable interface GPIF. The 8051 code can be downloaded from the USB interface or loaded via the I2C interface. SIE complete the serial data decoding, error control, bit filling is equal to the USB protocol related functions. Universal programmable interface (GPIF) can be seamlessly connected to other universal interfaces, such as ATA, UTOPIA, EPP, PCMCIA, and DSP processors.
In this design, SSOP56 encapsulated CY7C68013A is selected. The data bit width of the chip and the FPGA interface can be configured as 8 bits or 16 bits. At this time, the 8-bit bit width is selected, that is, PD0 ~ PD7 is connected to the FPGA as an interactive data line, while PD8 ~ PD11 is configured as I/O port and connected to the JTAG interface of the FPGA. The PC sends the data file to be burned and written to the USB chip through the USB2.0 interface. After the data is received by the USB chip, the four I/O port software PD8 ~ PD11 is used to simulate the JTAG time sequence conforming to the standard of IEEE STD 1149.1 to erase the configuration chip and program burn and write, so as to realize the remote online upgrade of the FPGA program.
Software design of the overall workflow, PC software and USB device connection is established, first distributed to the CY7C68013A firmware through USB interface, and then parse SVF file information, reassemble the packets into the JTAG need to send to the CY7C68013A under a machine, a machine under program receives the PC from the packet, according to the requirements of the JTAG state machine with the configuration of FLASH chip JTAG communication, after sending a communication result data to the upper machine, PC according to the result of communication decided to parse SVF file or an error.
CYPRESS company provides CY7C68013A chip firmware development kit, including the KEIL development environment and some of the routines, developers can provide the routine development of the new firmware, based on the official firmware program provides the functions of interface, through to add your code developed in these interface function, implementation needs to be completed by the function, make the development difficulty is reduced greatly. In this paper, the firmware mainly completes the connection with the upper computer, receives the data from the upper computer, and then simulates the JTAG timing through I/O to complete the data translation.
Here, I use Bulkloop engineering in the firmware development kit provided by CYPRESS to modify the functions of TD_Init () and TD_Poll () in the file of Bulkloop. The function of TD_Init () is only called once after USB startup. Add the corresponding initialization code in this function, which is processed before data is transferred, including IO port configuration, clock, endpoint, FIFO selection, and so on. Here, the CPU clock frequency is set to 48MHz, the USB working mode selects the port mode, TCK, TMS and TDI are set as the output port, TDO as the input port, EP2 sets the OUT breakpoint, and the FIFO size is double 512 bytes. EP8 sets the breakpoint IN, the FIFO size is double 512 bytes void TD_Poll (void), pollchinese for scheduling, this function is the user scheduler, USB will call this function repeatedly when idle, the code that needs to be executed repeatedly is put here. In bulkloop, it repeatedly receives upper computer data from endpoint 2 and then translates the command, simulates the JTAG sequence with GPIO port, reads the data from TDO port, transmits it to endpoint 8, and then transmits it to upper computer from endpoint 8.
After keil is successfully compiled to generate hex file, it needs to be converted into firmware in the form of bin file and provided to the upper computer for use.
When programming and developing the FPGA of XILINX company, the compiled Bit file is usually generated into the MCS file, and then the MCS file is written to the configuration chip using the JTAG download line. When developing the singing-writing tool, the serial vector file SVF file is generally used as the input. SVF is a syntactical specification that conforms to industry standard format to describe the operation of IEEE 1149.1 (JTAG) bus. SVF describes the operation of JTAG chain in a compact and portable form, and can program the XILINX device in JTAG chain by reading the information of SVF file. The iMPACT tool in XILINX's ISE software can generate an MCS file as an SVF file.
SVF file, in addition to setting the necessary conditions, there are only two real running commands. SIR sends commands to the IR register of the JTAG TAP state machine, while SDR sends data to the DR register of the JTAG TAP state machine. When writing, the input data is valid, while when reading, the output data is valid.
JTAG interface includes four signals: TMS, TDI, TDO and TCK, these signals and JTAG communication device on the chain, meet the provisions of the state of finite state machine 16, TMS signal control state, the conversion between the JTAG instructions and data by TDI pin into the device, TDO pin instructions and data from the receiving device, TCK is provide data interaction with synchronous clock.
All JTAG operations are to move data into or out of the JTAG instruction register (IR) and data register (DR), access to IR by shift-ir state machine, access to DR by shift-dr state machine, IR length is usually greater than 2 bits of arbitrary length.
The Cypress development kit provides a generic driver that communicates and controls with peripherals and user applications and, through the driver, reenumerates as a new USB device. The user operates the upper computer software to realize the online program upgrade. The upper computer software firstly establishes the connection with the USB device, automatically issues the firmware to CY7C68013A through the USB interface, analyzes the information in the SVF file, makes the data format conform to the data format required by the communication of the lower computer, sends it to the firmware program of CY7C68013A, and establishes the communication with it. This design USES C# to complete the interface development, including FLASH configuration chip erase, burn and verify functions.
PC the TIR, HIR, TDR and HDR these four commands to save value and significance to variable, when SIR command, in accordance with the order of the TIR + + HIR SIR assembled into a new data and length, namely 0 x3a3ca (26), after the assembly, increase the frame before data marks, command, data length, forming a new array, then the array through the USB to the send to 68013 a, 68013 a in firmware after receive the upper machine issued by running the driver in the firmware, after the endpoint receives the USB distributed data, Begins to judge the flag that the array frame is valid, and in turn determines the command flag.
If it is, SIR TMS to SHIFT from 1100 - IR state, assembled to SIR according to the sequence from low to high into the TDI, namely 01010011110001011100000000, one finally need to buy high TMS first and then into the TDI, finally TMS from 10 back to IDLE state.
When the upper computer executes the SDR command, it reconstitutes the new data in the order of TDR+SDR+HDR, i.e. 0x0006 (9 bits). If the command line contains TDO, it also needs to receive the return value. After the assembly, add the frame start mark, command mark and data length mark in front of the data to form a new array, and then send the array to 68013A through USB. When the 68013A firmware program receives the data, it starts to judge the valid flag of array frame, and then judge the command flag in turn.
If it is the SDR command, TMS will enter the shift-dr state from 100, and the assembled SDR will be sent to TDI from low to high, i.e. 011000000. The last digit needs to set the TMS high first and then send it to TDI.
The logic analyzer was used to grab the JTAG timing of SIR and SDR mentioned in the case. Since GPIO was used to simulate the JTAG timing, the code to simulate the JTAG timing was optimized to improve the rate, and the TCK frequency was not fixed, ranging from 500 KHz to 1 MHz. In the process of chartering, since each code block needs to be delayed for the end of chartering, the frequency of TCK has little impact on the overall chartering time. After testing, the chartering time of this method is basically the same as that of JTAG simulator, and the expected effect is achieved.
In this paper, the USB2.0 chip CY7C68013A is used to design an online upgrade method of FPGA program. The data sent by the host computer software from the USB interface is converted into signals conforming to the IEEE 1149.1 (JTAG) standard, and the erase, burn, write and verify of the FPGA configuration chip are completed, which provides an effective way for the online upgrade of FPGA program. This method does not need to disassemble the equipment, effectively reduces the maintenance cost, and can meet the needs of special applications.