• USB interface power arbitrary wave generator design

    • source: ivan;
    • Time: 5/26/2020 8:20:05 AM
  • 0 The introduction

    In the field of oil drilling, the short distance wireless transmission technology of downhole signals is not only helpful to replace the expensive special cable drilling tools with conventional drilling tools in the high frequency magnetic coupled channels, but also helpful to realize the measurement of near-bit parameters across the threaded drilling tools. Downhole wireless channel is composed of drilling fluid, drill string and formation. Similar to underwater acoustic channels. For the development of SDR transmitter for downhole wireless communication, it is necessary to realize all the functions except analog front end and digital-to-analog converter by software as much as possible.

    downhole SDR transmitter development of the conventional technical route is to use the upper computer to design signal modulation algorithm, and then the algorithm is transplanted to the microcontroller, field programmable logic array, digital signal processor and other embedded hardware, and then through the high integration transmitter output power signal. The algorithm can be verified by using any wave signal generator, such as Keysight 81150A impulse function and any noise generator, which can output any waveform signal with 14 bits, 512k sampling depth and 2GSa/s sampling rate. Due to the limited output power, the output power of the signal generator is only 0.25w even after adding the high-voltage option, which cannot meet the power demand of downhole SDR transmitter. Additional independent amplifiers can not meet the need of high integration of one-time hardware development and verification.

    the core hardware of the USB interface power arbitrary wave generator designed in this paper is exactly the same as that of downhole SDR transmitter, which avoids the secondary development and verification of the hardware. The upper computer writes the designed waveform data through the USB interface, and the power arbitrary wave generator realizes DAC, power amplifier, filter and other functions through a single high-integration chip. The output power is up to 6W. The power arbitrary wave generator can shorten the development cycle of SDR transmitter.

    1 Structure and principle

    Downhole high temperature and high pressure environment is a challenge to the reliability of electronic instruments. The reliability of downhole SDR transmitter can be improved by high temperature component selection and high integration design。

    Designed by Texas instruments, the AFE031 power line analog front-end chip has a temperature resistance of 125 ℃, and integrates DAC, PA, programmable gain amplifier, filter and other components internally. It is a high integration chip specially designed for power carrier communication. The frequency range meets the requirements of EN50065CENELEC A, B, C and D bands, and supports frequency shift keying, spread spread keying and orthogonal frequency division multiplexing modulation modes. The swing amplitude is up to 12V and pp at the output of 1.5a, which is especially suitable for driving low impedance lines. The core hardware of the USB interface power arbitrary wave generator designed in this paper is based on this chip, which is consistent with the structure of downhole SDR transmitter. External devices communicate with AFE031 internal registers and DAC via serial peripheral interface.

    The CP2130 bridge chip designed by the American chip lab allows the host computer to communicate with the SPI interface of AFE031 chip through the universal serial bus interface. Manufacturers provide windows-compatible API libraries and li-busb libraries for platforms such as Linux。

    Taking 150kHz as the highest transmitting frequency of downhole SDR transmitter, according to Nyquist sampling theorem, the sampling frequency cannot be lower than 300kHz. Since the upper computer is not a real-time operating system, the data written directly to the DAC of AFE031 via the cp2130uab-spi bridge chip cannot meet the demand of any waveform generator for rate and clock synchronization. After actual measurement, mainstream commercial computers using Windows10 operating system send instructions to CP2130 continuously through USB interface, one SPI output instruction updates DAC data once, and the minimum time interval of instructions is about 50 seconds. In other words, at this time, the update frequency of any waveform generator is lower than 20kHz, and the clock frequency cannot be kept constant. In order to solve this problem, the USB interface power arbitrary wave generator innovatively USES the large capacity synchronous high-speed advanced first out memory as the SPI interface data buffer, realizing: 1) the USB interface to download waveform data; 2)FIFO stores waveform data in SPI protocol format; 3)FIFO controls the process of DAC playback waveform data through SPI interface, which is controlled by upper computer without any embedded programming control. FIFO converts low-speed SPI input instructions into high-speed SPI output instructions, and controls the DAC inside AFE031 to generate signals and amplify the output through PA. AFE031 and its peripheral circuits comprise the same core hardware as downhole SDR transmitter.

    FIFO adopts IDT72V2111 chip of IDT company in the United States. The synchronous FIFO chip has a storage depth of 512k, which allows cascading expansion of storage depth and supports scalable 9-bit data storage. Three bits of data are selected to store the required process signals for SPI communication。

    The upper computer converts from USB interface to SPI interface through CP2130, and communicates with AFE031 through FIFO and SPI interface. The AFE031 has two communication modes: one is the read-write operation of the internal control register; The other is a write-only operation that DAC outputs. For the power arbitrary wave generator, the operation can be written to the internal control register many times to ensure that the write is correct, without reading operation. In this way, the SPI operation from CP2130 to AFE031 is a one-way data flow, and only CS, CLK and MOSI communication lines are needed to meet the FIFO first-in, first-out service conditions. The non-real-time SPI instructions sent by the upper computer are stored in FIFO and then sent to AFE031 in real time according to the required clock frequency, so as to set the specific data update frequency of the internal DAC of AFE031, that is, the sampling frequency of the signal.

    CP2130 has up to 11 output pins. In addition to being used for SPI operation, some pins are used as universal input and output pins to control FIFO operation, among which gpio.5 can be reused to output CLKOUT clock signal and provide a stable read-write clock for FIFO。

    2 The system design

    2.1 The hardware circuit

    CP2130 internal voltage regulator will be USB interface for 5VVBUSThe bus voltage is reduced to 3.45v VCCOutput to power all digital circuits. Using the default output port multiplexing setting, gpio.1 and gpio.1 respectively control the write enable and read enable of FIFO. The internal oscillator CLKOUT of the output frequency can be set by the frequency divider to provide a read and write clock for FIFO. FIFO completes the read and write operation on the rising edge of the clock. In addition, gpio.6 controls the DAC pin of AFE031 and selects the communication object that determines SPI interface: the control register of AFE031 or DAC。

    IDT72V2111 is D0-2It's a three-bit input of a FIFO,Q0-2It's a three-bit output of a FIFO。FWFT/SI pin grounding select standard FIFO mode, OE pin grounding enable FIFO output。

    AFE031 internal PA by external 15V VPAThe power supply。

    When the DAC pin is high, the control register can be read and written through the SPI digital interface. At low voltage, SPI interface communicates directly with DAC. The control register can be used to set the enabling or not of PA and Tx components.

    AFE031 supports two modes of operation: DAC and pulse width modulation. The former USES a built-in 10-bit DAC, while the latter outputs analog signals via PWM. When the 5th bit of the Enable1 control register is set to 1, the output end of the DAC is connected to the input end of TxPGA, and the DAC mode with lower signal distortion is used. For the low-frequency carrier frequency of downhole SDR transmitter, the 10-bit precision DAC can meet the demand.

    The cut-off frequency of the Tx low-pass filter is set to the CENELEC B, C and D bands through the Control1 register, with a maximum cut-off frequency of about 150kHz. The Tx_F_IN2 pin of the filter needs to be grounded, and the output passes through capacitor CINIt is directly connected to the PA input terminal and can also use an external low-pass filter as required。capacitance CINThe high-pass characteristic of the unipolar point is introduced for the transmission function of the amplifier, and its cut-off frequency is fHPAnd by theCINAnd the input impedance R of PAPAJointly set。

    Among them:CINThe unit isnF,RPAThe unit is kΩ,fHPThe unit is kHz。when CINWhen set to 3.3nF, the high-pass cut-off frequency is 2.4kHz。

    The power amplifier is a high voltage and large current inverting amplifier. The voltage gain is fixed at 6.5v /V, and the full power bandwidth is 300kHz. Setting the zero bit of the Enable1 register as 1 can enable the output, and the output can pass through RSETThe resistance sets the current limit. Limiting current ILIMDetermined by the following formula:

    Among them:RSETThe unit iskΩ,ILIMThe unit isA。

    The output voltage of DAC needs to match the power amplifier. GAIN se-lect register can be used to set the GAIN of TxPGA to 0.25, 0.5, 0.707 and 1V/V. TxPGA output is connected to Tx_F_IN1 pin of Tx filter.

    AFE031 internal transmitter PGA, transmitter filter and power amplifier are realized by operational amplifier.

    2.2 Update frequency with FIFO operation

    The FIFO reading and writing frequency of IDT72V2111 can reach up to 100MHz at most, and IDT72V211L20 of 50mhz can meet the demand. The SPI clock frequency of AFE031 is up to 20 MHz, and the data update rate of internal DAC is 1.5MSa/s. The clock frequency of SPI controller in CP2130 is up to 12MHz. The internal USB cable controller supports USB2.0 full speed mode up to 12Mbps.

    The DAC update for AFE031 requires only 10 bits of data, but the API library for CP2130 only supports byte sending。

    CS signal starts SPI transmission at a low level, reads MOSI data on the SCLK clock rising edge, sends 2 bytes of data, and then CS is pulled up again. Among them:TtIs the CS low-level time,TiIs the time interval between two consecutive instructions,Tb、Tm与TaIs the time interval before, during, and after 2 bytes of data. Due to the inability to obtain the internal logical chronological relationship of CP2130, each time interval was measured by using the upper computer to continuously send instructions to the 7 kinds of rate f allowed by CP2130 without SPI delay。

    If the output of CP2130SPI is directly connected to AFE031, the DAC of AFE031 completes data update at the rising edge of CS signal elevation. DAC update frequency fupdateDetermined by the following formula:

    Due to the TiAnd TaWith the increase of SPI clock rate f, the update rate of DAC increases slowly, and T is found in the measurementtThe measured value is also increasingly unstable, which means the stability of DAC update rate becomes worse. This conclusion is the same as the above analysis. The introduction of the buffer FIFO solves this problem.

    First, the FIFO ACTS as a buffer between slow writes and high reads. The SPI interface data of CP2130 is sent into FIFO according to the slower write clock that matches the SPI clock rate, and then the clock is read faster and sent to AFE031 to ensure the normal DAC update frequency. The reading and writing clock of FIFO is cp2130gpio.5 which is reused as CLKOUT. It is important to note that this clock is independent and not synchronized with SPI's SCK.

    First, the FIFO ACTS as a buffer between slow writes and high reads. The SPI interface data of CP2130 is sent into FIFO according to the slower write clock that matches the SPI clock rate, and then the clock is read faster and sent to AFE031 to ensure the normal DAC update frequency. The reading and writing clock of FIFO is cp2130gpio.5 which is reused as CLKOUT. It is important to note that this clock is independent and not synchronized with SPI's SCK。

    2.3 Upper computer software

    The CP2130 driver and link library for the upper computer software are provided by the American core laboratory. For Windows applications, the slab_usb_spi.dll API library and the C# demo program are provided, with the latter providing sample code for most function operations. The function is divided into data transmission and control transmission.

    This design USES VB.NET to complete the upper computer software of power arbitrary wave generator. For SPI communication Settings, the API library provides the CP213x_SetSpiControlByte control transfer function to set the SpiControlWord control word。

    With push-pull output mode, no pull-up resistance is required in the circuit。

    For SPI write operations, the API library provides the CP213x_TransferWrite data transfer function, written in bytes. A successful write returns USB_SPI_ERRCODE_SUCCESS。

    CP2130's GPIO pin can be configured by configuring its internal disposable programmable read-only memory, and the design USES the default configuration. CP213x_SetGpioModeAndLevel function is used to set the pin function and state. Through CP213x_SetClockDivider CLKOUT function set output frequency, due to set the frequency division coefficient, cannot guarantee the clock output step length constant, hang in USB interface at the same time without output.

    The program of power arbitrary wave generator is the read-write control of FIFO. The read-write clock is CLKOUT, gpio.1 as write enable and gpio.2 as read enable. After enabling, the process data of three SPI signal lines can be written or read。

    For periodic or repeated signals, the single cycle data instruction in FIFO can be re-sent through RT pin of IDT72V2111 without the need to input complete waveform data. As a FIFO readout clock, the output frequency of CP2130 internal oscillator CLKOUT is set by frequency divider. In order to realize any output period, it is necessary to set the sampling rate of single-period waveform data before writing the waveform instruction. The resend response time of IDT72V2111 is determined and meets the design parameter requirements.

    Through chip selection and program design, the maximum output power of this USB interface power arbitrary wave generator is 6W, with a 10-bit output precision, a sampling depth of 512k, and a maximum sampling frequency of 500kSa/s, which meets the design requirements of downhole SDR transmitter.

    3 test

    This USB interface power arbitrary wave generator can be used to produce the desired output waveform of up to 6W. The output power is determined by the set output signal amplitude. For periodic signals, the period can be determined by the output frequency of CLKOUT and the sampling point per period. The higher the output frequency and the lower the sampling point per cycle, the higher the output frequency.

    USES oscilloscope to measure the output through preset different waveforms. The output precision is consistent with the design and meets the design requirements. 100 KHZ sine wave output signal after plastic, fengfeng 10 v output values, the load Ω 50.

    this arbitrary wave generator has been used in the development of high frequency magnetic coupling cable drill pipe system. In the design of SDR high-power transmitter for short distance wireless transmission of downhole signals, the purpose of one-time hardware development and verification with high integration degree has been realized, which shortens the development time and brings great economic benefits.

    4 conclusion

    USB power arbitrary wave generator design based on the core department laboratory CP2130 USB - SPI bridge chip, the IDT e.g. IDT72V2111 synchronous FIFO chips and American Texas instruments AFE031 electric analog front-end chip, without embedded programming control, can realize the PC via USB download waveform data and through the function of the power amplifier output waveform signals. CP2130 bridge chip realizes the communication between USB interface of upper computer and power arbitrary wave generator, and FIFO chip plays a role in matching SPI communication speed and stabilizing DAC update rate. The high integration core hardware of AFE031 chip and its peripheral circuit is completely consistent with the downhole SDR transmitter, and the output power is up to 6W. The power arbitrary wave generator realizes one-time hardware development and verification, and shortens the development time of downhole SDR transmitter.